1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com ht19 features 350v breakdown voltage 18? maximum switch resistance current limiting protection operates at 2.3v input applications telephone handsets modems fax machines answering machines remote meter reading telephone interface products ? ? ? ? ? ? ? ? ? ? typical application circuit electronic telephone line switch tip ring tpg hk s gn d dp ls cs r se n 15 v tp tr ansient protection ht19 te lecom circuit general description the supertex ht19lg is an electronic line switch circuit that replaces the mechanical hook switch contact or a discrete hook switch in a telephone handset or modem. it switches the positive side of the telephone line using control inputs that are referenced to the negative side of the line. in its off state, it can withstand 350v on the positive input. in its on state, it has a maximum series resistance of 18?. the device provides current limiting determined by an external resistor. there are three control inputs. the hks pin turns on the hook switch when connected to the tpg pin. this can be accomplished by using a mechanical switch which closes when the handset is physically off-hook. the ls pin allows a logic signal to turn on the hook switch. the dial pulse, pin 6, is used to turn the hook switch off for pulse dialing. the dial pulse (dp) is active low.
2 ht19 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com ordering information device package option 8-lead soic (narrow body) 4.90x3.90mm body 1.75mm height (max) 1.27mm pitch ht19 HT19LG-G -g indicates package is rohs compliant (green) absolute maximum ratings parameter value v tpg , input line voltage +350v v tp , output line voltage +18v dp continuous input voltage +10v storage temperature -65c to +150c junction temperature +150c soldering temperature* +300c power dissipation 0.8w absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. * distance of 1.6mm from case for 10 seconds. pin con?guration sym parameter min typ max units conditions v tpg high voltage positive supply - - 350 v i tpg = 500a, hks, ls, dp = open circuit i tpg input leakage current - - 2.0 a v tpg = 100v, hks, ls, dp = open circuit - - 200 v tpg = 290v, hks, ls, dp = open circuit r sw tpg to tp switch resistance - - 18 v tpg = 17v, i tpg = 180ma, sw = on - - 18 v tpg = 3.0v, i tpg = 20ma, sw = on - - 30 v tpg = 2.3v, i tpg = 5.0ma, sw = on i tpg - i tp bias current - - 75 a v tpg = 5.0v, sw = on - - 100 v tpg = 10v, sw = on i lim i tpg current limiting 188 250 330 ma r ext = 200 1% i hks hks input current - - 200 a v hks = 40 to 70v i ls ls logic input current - - 30 a v ls = 3.0v i dp dp logic input current - - -30 a v dp = 0v v il(hks) hks input low 0 - 0.2 v v tpg = 3.0 to 70v v ih(hks) hks input high 2.0 - v tpg v v tpg = 3.0 to 70v v il(ls) ,v il(dp) input logic low for dp and ls 0 - 0.2 v v tpg = 3.0 to 70v v ih(ls) ,v ih(dp) input logic high for dp and ls 1.5 - 10 v v tpg = 3.0 to 70v t on turn-on time - - 1.0 ms v tpg = 4.5v t off turn-off time - - 1.0 ms v tpg = 4.5v electrical characteristics (t a = 25c unless otherwise speci?ed) product marking y = last digit of year sealed ww = week sealed l = lot number = green packaging yyww ht19 llll 1 2 3 4 8 7 6 5 gnd dp nc ls tpg hks tp cs 8-lead soic (narrow body) (lg) (top view) 8-lead soic (narrow body) (lg) package may or may not include the following marks: si or
3 ht19 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com logic truth table z = high impedance, open circuit x = irrelevant l = logic level low h = logic level high block diagram hks ls dp switch state h l or z h or z o n h h h or z on l or z l or z h or z off l or z h h or z on x x l off tpg tp cs gn d hk s ls dp h = on l = off (1) (2) (5) (6) (8 ) (7 ) (3 ) charge pump and logic control pin description pin name description 1 tpg positive input side of a telephone line, typically tip side. 2 hks hookswitch input. connect hks to tpg to turn on the hook switch. internally pulled low with a high value resistor. 3 gnd device ground. negative side of a telephone line, typically ring side. 4 nc no connect. open circuit. no internal connections to the device. 5 ls line switch input. input logic high turns on the hook switch. internally pulled low with a high value resistor . 6 dp dial pulse input. input logic low turns off the hook switch. used for pulse dialing. internally pulled high with a high value resistor. 7 cs current sense input. an external resistor connected between cs and tp sets the current limit. 8 tp positive output side of a telephone line. zener protection to prevent this output from rising above 18v is required.
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate product liability indemnification insurance agreement. supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc. website: http//www .supertex.com . ?2009 all rights reserved. unauthorized use or reproduction is prohibited . 1235 bordeaux drive, sunnyvale, ca 94089 te l: 408-222-8888 www .supertex.com 4 ht19 (the package drawing(s) in this data sheet may not re?ect the most current speci?cations. for the latest package outline information go to http://www.supertex.com/packaging.htm l .) doc.# dsfp-ht19 a081109 8-lead soic (narrow body) package outline (lg) 4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch 1 8 seating plane gauge plane l l1 l2 e e1 d e b a a2 a1 seating plane a a to p v iew side v iew vi ew b vi ew b 1 note 1 (index area d/2 x e1/2) vi ew a-a h h note 1 symbol a a1 a2 b d e e1 e h l l1 l2 1 dimension (mm) min 1.35* 0.10 1.25 0.31 4.80* 5.80* 3.80* 1.27 bsc 0.25 0.40 1.04 ref 0.25 bsc 0 o 5 o nom - - - - 4.90 6.00 3.90 - - - - max 1.75 0.25 1.65* 0.51 5.00* 6.20* 4.00* 0.50 1.27 8 o 15 o jedec registration ms-012, variation aa, issue e, sept. 2005. * this dimension is not speci?ed in the jedec drawing. drawings are not to scale. supertex doc. #: dspd-8solgtg, version i041309. note: this chamfer feature is optional. a pin 1 identi?er must be located in the index area indicated. the pin 1 identi?er can be: a molded mark/identi?er; an embedded metal marker; or a printed indicator. 1.
|
